(1) Technical Field
This invention relates to electronic circuits, and more particularly to circuits and methods for improving electrostatic discharge (ESD) tolerance and switching speed in integrated circuits (ICs), such as ICs for radio frequency (RF) signal switching or processing.
(2) Background
The design of integrated circuits (ICs), particularly ICs for radio frequency (RF) signal switching or processing, often requires trading off or balancing different performance and functional parameters. For example, a conventional RF signal switch IC capable of switching at high speed may exhibit poor linearity, while a highly linear RF signal switch IC may be only capable of switching at much lower frequencies.
As another example, providing protection against ESD events (e.g., static electricity discharge that may be generated by a human body or other sources) is important in designing ICs, particularly ICs that include field effect transistors (FETs), which are notoriously susceptible to permanent damage when subjected to high voltages. For example, a human body induced ESD event may reach 15,000 volts or more and have a short rise time, on the order of nanoseconds. Such an ESD event may cause damage to a FET (e.g., gate-oxide punch-through), especially complementary metal-oxide-semiconductor (CMOS) FETs, metal-oxide-semiconductor FETs (MOSFETs), and other types of FETs, particularly those fabricated on semiconductor-on-insulator (“SOI”) and silicon-on-sapphire (“SOS”) substrates. However, providing adequate ESD guard circuitry or structures in an IC may affect other circuit parameters, such as switching time.
Accordingly, it may be desirable to improve both ESD tolerance and switching time for semiconductor devices while achieving high linearity, particularly in FETs fabricated on SOT and SOS substrates. The present invention provides system, apparatus, and methods for improvement of both ESD tolerance and switching time in such devices.